T-junctions are widely used to interconnect three wires in wiring levels of integrated circuits. At high frequencies T-junctions must be modeled in order to simulate layout parasitics as part of the performance check of the circuit. Not only are these simulations complex and time-consuming, but also the models generated are not scalable so the process must be repeated as layout groundrules by level or technology change. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.